Challenging career position in CMOS Circuit Design / ASIC design / circuit synthesis or functional/timing verification / Chip Level P&R domain where I can best utilise my Hardware and Software skills and with my competency and hard work expand and build further upon my skills as an experienced Development Engineer in VLSI industry.Expertise (Tools and Languages)
: Cadence DFII(Virtuoso 4.3&4.4), Duet Grafedit, Fujitsu
P&R tools : Duet Epoch, Fujitsu Gloscad&Lcadfe, Cadence Silicon
Migration tools : Duet Masterport
Characterization tools : Avant! MTB, Fujitsu CELZO
Simulation tools : Avant! HSpice, Avant! awaves
Verification tools : Cadence Dracula, Diva (DRC & LVS)
Extraction tools : Cadence Dracula LPE
HDLs known : VHDL, Verilog
Synthesis tools : Viewlogic Synthesizer
A Circuit Design engineer, working with DUET Technologies Inc., USA, with almost two years of experience in back end CMOS circuit design. Conversant with CMOS Circuit Design Methodologies, physical Layout architectures, Verification tools, P&R tools and a few HDLs. The experience includes developing IO libraries which involves design/simulation of the circuits, layout, layout verification, characterization, modeling and also migration of existing libraries across technologies/foundries.Work Experience
MasterPort porting tool, Virtuoso Layout editor, (Dracula Verification & Extraction), MTB Characterization tool, HSpice simulation tool. The library is targeted to have Bi-directional, Tristates, Inputs of different drive strengths and other optional functionalities like Pullup/Pulldown and/or schmitt. Other cells in the library include corner, power, ground, power clamp, rail splitter and spacer cells.The ruleset study and the initial ESD planning is in progress.
MasterPort porting tool, Grafedit & Virtuoso Layout editors, (Dracula Verification & Extraction), MTB Characterization tool, HSpice simulation tool. The job included migration of an I/O library across foundry to IBM6SF and Chartered 0.24u processes. The 40 cell library consisting of Bidirectionals, Tristates, Input, PCI, corner, power, ground, power clamp, rail splitter and spacer cells developed in TSMC.25u technology was to be migrated to IBM 0.24u and CS 0.24u processes.
MasterPort porting tool, Grafedit Layout editor, Dracula (Verification & Extraction).The job included setting up a flow through which IOs can be migrated from one ruleset to other using Masterport. Masterport was previously used to migrate Standard cells only and could not handle IOs. A methodology was created integrating Masterport with certain TCL/TK scripts so as to facilitate IO migration. The IO had to be broken down into various parts/tiles. After migrating those tiles separately, certain scripts were used to place those different tiles and generate the non migrated parts( like Guard Rings) on the top level. The routing was also done on the top level using TCL script.
Hspice simulation tool, Virtuoso Layout editor, Dracula (Verification & Extraction) tool, MTB Characterization tool..The job included development of DUET's internal I/O library consisting of 40 cells which include (Schmitt / Non Schmitt , OVT/ NonOVT) - Bidis, Outputs, Inputs, PCIs (66MHz), corner, power, ground, power clamp, rail splitter and spacer cells. The design flow included simulation(ckt design), preparation of physicals, Dracula verification of the physicals, electrical qualification of the extracted netlists, MTB characterization, LEF creation & validation and Databook creation.
Virtuoso Layout editor, CELZO characterization and modeling tool, Hspice simulation tool, Dracula verification tool, Gloscad & Lcadfe P&R tools.The job included designing, characterizing and modeling six I/O Buffers(PCI, 66 MHz) for Fujitsu. The buffers were designed in 0.25u technology with the functional and timing verification done using Celzo and P&R verification was done using Gloscad&Lcadfe.
Virtuoso Layout editor, CELZO characterization and modeling tool, Hspice simulation tool, Dracula verification tool, Gloscad & Lcadfe P&R tools.The job included designing, characterizing and modeling six I/O Buffers(5v tolerant PCI, 33 MHz) for Fujitsu. The buffers were then tested for their timing and functional performance using Celzo and P&R verification was done using Gloscad&Lcadfe.
ViewLogic VHDL compiler and synthesizer, XILINX libraries. Developed on a stand alone system (Pentium based PC).The design procedure was carried out by first individually simulating separate blocks used in the main design, and then integrating them into a single entity by using schematic capture. Viewlogic tools were used to analyze and pre simulate the design and the synthesis was done using Xilinx models.Software skills
Systems worked on
: SUN Workstations , Pentium based PC.
Operating Systems : SUN-OS 4.x/5.x(Solaris), DOS, UNIX, Novel Netware.
Software Languages known : C, BASIC, FORTRAN-77.
Windows Dev. Env. : MS Windows-3.1/95, X-Windows, Open Windows.
Scripting Language known : TCL / TK
-Bachelor of Technology in Electronics from Aligarh Muslim University, UP, INDIA (CPI : 9.78/10.0)
-High School from Our Lady
of Fatima High School, UP, INDIA (78% aggregate)
- H1B visa valid through Apr'2000.
References available upon request